It is well known that address transition detection circuits are widely used in semiconductor memories, e.g., read only memories, in order to control internal accessing circuits (e.g. sense amplifier circuits) in an appropriate processing timing, which enhances a sensing speed for stored data and actuates a generation of plural control signals. An address transition detection circuit senses a variation of an external address signal and then generates a master signal informing the address transition. All of control signals employed in performing a sensing operation in a memory device are made from using the master signal, e.g., delaying therefrom or combining therewith, generated from the address transition detection circuit. The ATD-oriented control signals with their own pulse widths and delaying terms between them, independently of an external operating frequency, are fixed into constant values, once after being manufactured, in accordance with a demand of a circuit designing.
In a sensing operation of a read only memory, as one sensing cycle which designates the period from beginning of the sensing operation to latching a result of the sensing is always constant, it would be possible to select a weak cell or to latch distorted sensing data nevertheless of a later sensing timing due to a power noise or a timing variation. Such mis-matched phenomena between the control signals and sensing cycle time causes the yield of a memory device to be reduced. And, a new demand for a sensing time shorter than a designed specification for a sense amplifier might need a newly modified circuit for the address transition detection.
For the purpose of enhancing an operating frequency of an asynchronous memory device, a synchronous memory has been regarded to as an useful way in a high bandwidth memory operation. Since the synchronous memory performs internal operations in response to a system clock which has a predetermined pulse width and frequency and the system clock is assigned to one of several frequency options, the control for the sense amplifiers must be designed to be cooperated with a frequency out of the system clocks.